The present invention generally relates to driver circuits, and more particularly to a constant voltage drive type driver circuit which outputs pulses having a regular peak value to a load impedance on a winding of a pulse transformer.
The integrated services digital network (ISDN) is a digital network capable of integrally handling various services such as telephone, facsimile communication, data communication and image communication. The reference points of the multi-purpose user/network interface of the ISDN are defined as shown in FIG.1 in the CCITT Recommendations of the Series I.
In FIG. 1, line terminating equipment (NT1) 1 terminates a digital subscriber line 4 from a switching system 5. The NT1 synchronizes the line, supplies power and also has other electrical connecting functions. Terminal equipment (NT2) 2 has a line connection control function. Standard terminal equipment (TE1) 3 has terminal functions in conformance with the CCITT Recommendations of the Series I Interface. T and S reference points are defined as shown in FIG. 1. The T reference point is a point between the user side and the network side, and the S reference point is a point between the NT2 2 and the TE1 3. Although not shown, an R reference point is set between a terminal adapter and existing terminal equipment.
A constant voltage drive type driver circuit (e.g., FIG. 2) is provided at the S and T reference points (see FIG. 1) of the ISDN. In other words, the constant voltage drive type driver circuit is provided at the output end of the NT1 1 on the side of the NT2 2, at the output ends of the NT2 2 on the sides of the NT1 1 a and the TE1 3, and at the output end of the TE1 3 on the side of the NT2 2.
The constant voltage drive type driver circuit must be designed so that the waveform of output pulses thereof is within a regular tolerable range.
FIG. 2 shows an example of a conventional driver circuit. In FIG. 2, a first reference voltage source 6 generates a first reference voltage V.sub.R1, and a second reference voltage source 7 generates a second reference voltage V.sub.R2, where V.sub.R1 &gt;V.sub.R2. The switching of analog switches S1 and S4 is controlled by a first control signal A, and the switching of analog switches S2 and S3 is controlled by a second control signal B.
A pulse transformer 8 has a primary winding L1 and a secondary winding L2, where the turn ratio of the windings L1 and L2 is set to n:1. An equivalent load impedance R.sub.L which exists when the line side is viewed from the pulse transformer 8, is connected to the secondary winding L2. In other words, the load impedance R.sub.L is connected across terminals of the secondary winding L2 when the impedance of the secondary winding L2 is neglected. One end of the primary winding L1 is coupled to the reference voltage source 6 via the analog switch S1 on one hand, and is coupled to the reference voltage source 7 via the analog switch S3 on the other. In addition, the other end of the primary winding L1 is coupled to the reference voltage source 6 via the analog switch S2 on one hand, and is coupled to the reference voltage source 7 via the analog switch S4 on the other.
Next, a description will be given of the operation of the driver circuit shown in FIG. 2. The first control signal A is a digital control signal for transmitting an upward pulse to the line, and the second control signal B is a digital control signal for transmitting a downward pulse to the line. The first and second control signals A and B will not assume a high level at the same time, but may assume a low level at the same time.
First, when the first control signal A assumes a high level as indicated by a1 in FIG. 3(A), the analog switches S1 and S4 turn ON as indicated by c1 in FIG. 3(C). In this state, the second control signal B assumes a low level as indicated by b1 in FIG. 3(B). Hence, the analog switches S2 and S3 are OFF as indicated by d1 in FIG. 3(D). Accordingly, the reference voltage VR1 is applied to one end of the primary winding L1 of the pulse transformer 8 via the analog switch S1, and the reference voltage V.sub.R2 is applied to the other end of the primary winding L1 via the analog switch S2. A current i1 flows through the primary winding L2 in a direction indicated by an arrow in FIG. 2.
Pulses having a peak value V.sub.RL described by the following formula (1) are output to the load impedance R.sub.L connected to the secondary winding L2 of the pulse transformer 8. Since V.sub.R1 &gt;V.sub.R2, the peak value V.sub.RL of the output pulses is a positive (upward) pulse as indicated by e1 in FIG. 3(E). EQU V.sub.RL =(V.sub.R1 -V.sub.R2)/n (1)
Next, when the first control signal A assumes a low level as indicated by a2 in FIG. 3(A), the analog switches S1 and S4 turn OFF as indicated by c2 in FIG. 3(C). As a result, a voltage is no longer applied to the primary winding L1 of the pulse transformer 8, and the peak value V.sub.RL of the output pulses becomes zero as indicated by e2 in FIG. 3(E).
When the second control signal B assumes a high level as indicated by b2 in FIG. 3(B), the analog switches S2 and S3 turn ON as indicated by d2 in FIG. 3(D). Hence, a current flows through the primary winding L2 in a direction opposite to the direction of the arrow shown in FIG. 2, and the pulses having a negative peak value V.sub.RL described by the formula (1) is obtained at the secondary winding L2. As a result, a negative (downward) pulse is applied to the load impedance R.sub.L as indicated by e3 in FIG. 3(E). That is, the peak value V.sub.RL of the output pulses is a negative (downward) pulse.
Next, when the first control signal A assumes the high level as indicated by a3 in FIG. 3(A), the second control signal B assumes the low level. Thus, similarly as described above, the analog switches S1 and S4 turn ON as indicated by c3 in FIG. 3(C) and the analog switches S2 and S3 turn OFF as indicated by d3 in FIG. 3(D). Accordingly, the peak value V.sub.RL of the output pulses is a predetermined positive (upward) pulse as indicated by e4 in FIG. 3(E).
Therefore, the data to be transmitted are output from the pulse transformer 8 to the load impedance R.sub.L as output pulses having the peak value V.sub.RL, that is, in the form of a bipolar code, depending on the first and second control signals A and B.
However, according to the conventional driver circuit shown in FIG. 2, the analog switches S1 through S4 may turn OFF at the same time. In this case, the terminal at the primary winding L1 of the pulse transformer 8 assumes a high impedance state. For this reason, when the driver circuit on the side of the load impedance R.sub.L is viewed from the side of the primary winding L1 of the pulse transformer 8, the equivalent circuit becomes as shown in FIG.4. The equivalent circuit shown in FIG.4 is a parallel circuit including a leakage inductance L of the pulse transformer 8, a line capacitance C and an impedance R.sub.L of the load impedance R.sub.L.
Accordingly, immediately after the analog switches S1 and S4 (or S2 and S3) undergo a transition from the ON state to the OFF state in a state where the analog switches S2 and S3 (or S1 and S4) are OFF, the parallel circuit shown in FIG. 4 functions as a damped oscillation circuit and discharges the charge which is stored in the line capacitance C when the impedance of the load impedance R.sub.L is small. In this state, an undershoot is generated at the falling edge of the output pulse as indicated by a solid line in FIG. 5.
In FIG. 5, the solid line indicates the output pulse obtained in the conventional driver circuit, and a one-dot chain line indicates ideal output pulse. The rising edge of the output pulse obtained by the conventional driver circuit is approximately the same as that of the ideal waveform. However, since the undershoot occurs at the falling edge for the reason described above, there is a problem in that a noise is generated thereby. Particularly, there is a problem in that the pulse mask prescribed under Section 8.5.3 of the CCITT Recommendations of the Series I.430 cannot be satisfied at the S and T reference points of the ISDN.